[SI-List] Embedded capacitance for decoupling

2017-06-30 by:CAE仿真在線來源:互聯網

Can the capacitance realized by embedding capacitance in the PCB stackup replace discrete decoupling capacitors?

Let's say the discrete decoupling solution for a processor's Vcore rail has thirty 0.22 uf Hi-F caps. Is there a practical way to use an embedded passives approach in the PCB stackup to achieve the needed decoupling capacitance and thus remove these thirty discrete capacitors?

If so, are there any papers published around this? (I've searched and can't find anything substantial on replacing discrete ceramic capacitors with embedded PCB capacitance.)

Thanks,

Jim Peterson

Honeywell Aero

Use the search term "embedded capacitance pcb structures" to bring up a wealth of information.

Capacitance of parallel plates with dielectric is C=k*E0*A/d where E0 is the permittivity of space (close enough to air) which is 8.854e-12, k is dielectric constant (of FR4: about 4.5), A is Area of the plates and d is separation between the plates.

So, how much area on two adjacent layers are you willing to devote to this?

I'll pick a really large guess: how about a square 30cm on each side, so the Area is 900 cm^2, I'll also be generous and say there are only 0.2mm between those planes.

So:

C=4.5*8.845e-12*0.09m^2/2e-4=0.01793uF

thirty 0.22uF capacitors total 6.6uF.

SO, you need about 370 times more capacitance than a 30cm*30cm square with 0.2mm separation gives. You almost certainly don't have enough layers or enough area to get there.

In short: no, the capacitance realized by embedding capacitance in the PCB stackup can not (reasonably) place thirty 0.22uF caps.

--- Joe S.

Joseph-

Your conclusions are OK, if you are assuming a dielectric constant of PCB material and a thicknesses associated with PCB stackups.

However the embedded capacitance materials that several vendor supply have a dielectric constant in the range of about 15 to 25 and thicknesses in the 6um-15um range. The typical capacitances available range from 6-20 nf/in^2 .

Check out the offerings by 3M, Oak-Mitsui and others for examples.

Regards,

-Ray Anderson

Xilinx Inc.

I'll also add that there is a temporal element to this- at some point due to the travel time of wavefronts, the change-in-charge signal at the hinterlands of the capacitor are no longer in phase with the signal at the ports of the capacitor. This means that a large area capacitor is a lot less effective than a "folded" or multi-plate capacitor at a given frequency.

I am constantly reminding people that PCB planes are just higher order transmission lines or waveguides. It's easy to forget that due to their typically low z0 and shape. Just like in the transition from "wire" to "transmission line" mode of thinking, you have to transition from "capacitor" to "charge line".

Regards,

Josiah Bartlett

Principal Engineer

Tektronix, Inc.

The dielectric constants of the materials commonly called "FR-4" with a resin content that works for these purposes is rarely over 4. Usually more like 3.8. As a side note, FR-4 does not specify a material. It specifies a UL flame retardant class.

Wonder when we will cease using only the term FR-4 to call out a material. If that is all that is on the fab drawing it is possible to get more than 30 different PCBs, all of which satisfy this spec.

Lee Ritchey

Jim,

As usual, there is no single yes or no answer to this question, because the correct answer depends on many factors.

But contrary to popular belief, my general answer is that yes, it is possibly in a number of circumstances, maybe in a surprisingly large percentage of all possible cases, to reduce the number of discrete capacitors by using embedded capacitance (and below you will see that it is really about inductance, not capacitance). If we put aside several other questions such as cost and focus only on the electrical performance of the supply rail in question, we first need to look at the existing design. There are thirty pieces of 0.22uF capacitors, called Hi-F, which I assume means they are small-size surface-mount capacitors. Why do we have thirty of them???? For their capacitance, which, without any DC or AC bias or any other derating, gives us a mere 6.6uF nominal capacitance? If we need 6.6uF capacitance, we can get it today from a single small-size ceramic capacitor, we dont need thirty pieces... Assuming that the starting design is good and the design had thirty pieces for a good reason, we can quickly convince ourselves that likely the number of small capacitors is dictated by the total inductance we want to achieve by them, not by their total capacitance. Using very simplistic numbers and assuming that the loop inductance from a single 0.22uF capacitor is 1nH, thirty of them will give us 33pH cumulative inductance, which just happens to be the square inductance of a 1-mil (25um) laminate. So all thirty 0.22uF capacitors can be left out and replaced by a 1-mil laminate. Of course the laminate capacitance, dependent on its size, will be just a few nF or maybe up to a few hundred nFs for large laminates, so we will need to add capacitance, but likely we can do it with much fewer components, under some circumstances using just bulk capacitors.

Details of actual situations can vary a lot, and for a careful design we need to look at the whole picture, all constraints and all requirements. It is true that time-of-flight for available charge will eventually matter, but this opens up another discussion: time of flight matters more as the mismatch between PDN components is increased, and it matters less, and eventually it does not matter at all, for matched structures. For largely mismatched structures it is easy to show that the location of available charge, whether it is from a laminate or from a capacitor, matters.

Regards,

Istvan Novak

Oracle

Jim,

Google "Steve Weir Interra" and you will get some excellent papers and presentations on the how and why of the power of reducing the inductance of your PDS.

Aubrey

I think the objective of removing the 0.22uF capacitors & intention to convert them into embedded type is not clear..

if miniaturisation of the overall PCB system is the final goal, there are plenty of other methods...

regarding embedded caps in the PCB :

1) PCB manufacturer should be consulted about the availability of high dielectric constant material. Normally they have material of dielectric constant value ~10 in the stock. other high value dielectric materials needs to be specially ordered and hence expensive.

2) converting 0.22uF cap into embedded type is not feasible. Maximum attainable value is 20nF/inch^2 using 3M C2006 material.

3) once someone decides to move to embedded type from discrete caps, existing 0.22uF decap requirement may change to some other cap value. This requires detailed PDN investigation and evaluate the required decap number for embedded decap scenario.

Thanks

Sanjeev

Getting embedded capacitance by using planes and cores/prepregs is great (and generally free) but it is not the only way to embed capacitance in a PCB. Some companies like Wurth can also embed physical components inside the laminate which the becomes rather thicker than normal. One of the benefits of this is that you can then use microvias directly on to the capacitors and so remove some of the problem of the connecting wire inductance. Has anyone got any measured data on how this approach can help PDN design?

Regards

Jonathan

Dear Istvan,

Thank you for your very detail explanation for 30 caps vs plane capacitance. I guess this is the direct consequence of the frequency vs impedance curve of a capacitor going up above the resonance frequency. Above the resonance frequency it is the inductance and not the capacitance that determines the over all impedance, thus increasing capacitance does not lower impedance but reducing inductance does.

Later on you discussed matched vs mismatched PDN components. Unfortunately I am not familiar with this term and cannot visualize the circuit make up of this. I

Wonder if you could expand the concept a bit? Thank you very much.

Best Regards,

Alfred Lee

Lee,

With the permittivity of a PCB material 3.8 at 1 GHz and loss tangent 0.02, permittivity at DC or at lower frequencies is about 4.57 and drops with the frequency. With 3.8 at 10 GHz and same loss tangent, permittivity at DC can reach 4.7. To have Dk at DC below 4 with 3.8 at 1 GHz, the loss tangent should be below 0.005. This follows from the basic relaxation polarization property of the composite materials, confirmed with multiple experiment.

Best regards,

Yuriy

I have written numerous papers on how planar embedded capacitance can successfully be used to remove large numbers of discrete decoupling capacitors in high speed digital designs. The papers include data from Sun, Huawei, H.P., IBM, Nortel and others. Just Google my name and many of them should be available. Some of the data is also available of the 3M web site under Embedded Capacitance Material or ECM.

Joel Peiffer - 3M

Hi Joe,

The below calculations are not relevant to decoupling on high speed digital designs because they are not taking the C, L and R frequency effects into account. Embedded Capacitance works extremely well at higher frequencies by two modes.

One is supplying the charge much faster than discretes because of the lower loop inductance (thus less noise generation). The second is driving large copper losses at high frequencies due to the mutual inductance of the closely spaced planes to dampen any resonances.

What is commonly found on embedded capacitance with very closely spaced planes (< 20 um and preferably high Dk) is that only 1% to 10% of the SMT capacitance is needed to significantly lower the noise with the use of embedded capacitance.

If the power bus noise is a large contributor to EMI, then EMI can be greatly reduced as well.

Regards, Joel

Hi Jonathan,

Yes, embedding discrete components can be utilized as well. There areadvantage and disadvantages of using embedded discrete components. One of thedisadvantages is that you still have the high inductance of the discrete component.

Regards,

Joel

Hi Alfred,

In a nutshell: as it was pointed out in this discussion, planes are still transmission lines, just not the usual one-dimensional traces or cables we may be accustomed to. They also have an approximate characteristic impedance. Just like with traces, if the transmission line is heavily mismatched, there will be standing waves. The bigger the mismatch, the bigger standing waves we get and the more the impedance will be location dependent. In the extreme case of matched planes, there is no (or very little) standing wave and the location does not matter; we dont need to worry about how close or how far the components are from each other.

Regards,

Istvan Novak

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